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HFA1110/883
November 1998
750MHz, Low Distortion Unity Gain, Closed Loop Buffer
Description
The HFA1110/883 is a unity gain, closed loop buffer which achieves a high degree of gain accuracy, wide bandwidth, and low distortion. Manufactured on Intersil's proprietary complementary bipolar UHF-1 process, the HFA1110/883 also offers very fast slew rates, and high output current. Component and composite video systems will also benefit from this buffer's performance, as indicated by the excellent gain flatness, and 0.04%/0.025 Degree Differential Gain/Phase specifications (RL = 75). For buffer applications desiring a standard op amp pinout, or selectable gain (-1, +1, +2), please refer to the HFA1112/883 and HFA1113/883 (featuring programmable output clamps) datasheets.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Fixed Gain of +1 * Wide -3dB Bandwidth . . . . . . . . . . . . . . . 750MHz (Typ) * Very Fast Slew Rate . . . . . . . . . . . . . . . . 1250V/s (Typ) * Low Differential Gain and Phase . . . 0.04%/0.025 Deg. * Low Distortion (HD3, 30MHz) . . . . . . . . . . -80dBc (Typ) * Excellent Gain Flatness (to 100MHz) . . . 0.03dB (Typ) * Excellent Gain Accuracy . . . . . . . . . . . . . . 0.99V/V (Typ) * High Output Current . . . . . . . . . . . . . . . . . . 60mA (Typ)
Applications
* Video Switching and Routing * Pulse and Video Amplifiers * Wideband Amplifiers * RF/IF Signal Processing * Flash A/D Driver * Medical Imaging Systems
Ordering Information
PART NUMBER HFA1110MJ/883 TEMP. RANGE (oC) -55 to 125 PACKAGE 8 Ld CERDIP PKG. NO. F8.3A
Pinout
HFA1110/883 (CERDIP) TOP VIEW
V+ OPT V+ NC IN
1 2 3 4
8
OUT NC OPT VV-
-+
7 6 5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number
1
511083-883 File Number 3620.2
HFA1110/883
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Voltage at Input Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VOutput Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .55mA ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Information
Thermal Resistance (Typical, Note 1) JA(oC/W) JC(oC/W) CERDIP Package . . . . . . . . . . . . . . . . 120 35 Maximum Package Power Dissipation at 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W Package Power Dissipation Derating Factor above 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3mW/oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Storage Temperature Range . . . . . . . . . . . . . . . -65oC TA 150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . 300oC
Operating Conditions
Supply Voltage (VS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V RL 50 Temperature Range . . . . . . . . . . . . . . . . . . . . . -55oC TA 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VSUPPLY = 5V, RSOURCE = 0, RL = 100, VOUT = 0V, Unless Otherwise Specified. PARAMETER Output Offset Voltage SYMBOL VOS CONDITIONS VCM = 0V GROUP A SUBGROUPS 1 2, 3 Power Supply Rejection Ratio PSRRP VSUP = 1.25V V+ = 6.25V, V- = -5V V+ = 3.75V, V- = -5V VSUP = 1.25V V+ = 5V, V- = -6.25V V+ = 5V, V- = -3.75V VCM = 0V 1 2, 3 1 2, 3 1 2, 3 Input Current Common Mode Rejection Input Resistance CMSIBP VCM = 2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V Note 2 1 2, 3 1 2, 3 Gain (VOUT = 2VP-P) AVP1 VIN = -1V to +1V 1 2, 3 Output Voltage Swing VOP100 RL = 100, VIN = +3.3V 1 2, 3 VON100 RL = 100, VIN = -3.3V 1 2, 3 Output Voltage Swing VOP50 RL = 50, VIN = +2.7V RL = 50, VIN = +3.3V 1 2 3 VON50 RL = 50, VIN = -2.7V RL = 50, VIN = -3.3V 1 2 3 TEMPERATURE (oC) 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125, -55 25 125 -55 25 125 -55 MIN -25 -40 39 35 39 35 -40 -65 25 20 0.980 0.975 3 2.5 2.5 2.5 1.5 MAX 25 40 40 65 40 50 1.020 1.025 -3 -2.5 -2.5 -2.5 -1.5 UNITS mV mV dB dB dB dB A A A/V A/V k k V/V V/V V V V V V V V V V V
PSRRN
Input Current
IBSP
RIN
Spec Number 2
511083-883
HFA1110/883
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: VSUPPLY = 5V, RSOURCE = 0, RL = 100, VOUT = 0V, Unless Otherwise Specified. PARAMETER Output Current SYMBOL +IOUT CONDITIONS Note 3 GROUP A SUBGROUPS 1, 2 3 -IOUT Note 3 1, 2 3 Quiescent Power Supply Current ICC RL = 100 1 2, 3 IEE RL = 100 1 2, 3 NOTES: 2. Guaranteed from Input Common Mode Rejection Test, by: RIN = 1/CMSIBP. 3. Guaranteed from VOUT Test with RL = 50, by: IOUT = VOUT/50. TABLE 2. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 4. PDA applies to Subgroup 1 only. SUBGROUPS (SEE TABLE 1) 1 1 (Note 7), 2, 3 1, 2, 3 1 TEMPERATURE (oC) 25, 125 -55 25, 125 -55 25 125, -55 25 125, -55 MIN 50 30 14 -26 -33 MAX -50 -30 26 33 -14 UNITS mA mA mA mA mA mA mA mA
Spec Number 3
511083-883
HFA1110/883 Test Circuit (Applies to Table 1)
V+ ICC + 10 0.1
VOS = 0.1 510 1 VIN 0.1 100K (0.01%) 1 K1 2 5 100 100 4 8 DUT 470pF + x100 510 1K VOUT VY
VY 100
VZ IBIAS = 100K VZ
K3 + HA-5177 0.1 + 10 0.1
IEE
V-
NOTE: All Resistors = 1% () All Capacitors = 10% (F) Unless Otherwise Noted Chip Components Recommended
Spec Number 4
511083-883
HFA1110/883 Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3) AV = +1 TEST CIRCUIT
V+ 1 VIN RS 50 V4 5 8 50 50 VOUT 2
NOTE: VS = 5V RS = 50 RL = 100 For Small and Large Signals
VOUT +2.5V 90% 90% +2.5V
VOUT 250mV 90% -SR 10% 10% -2.5V tR , +OS -250mV 10% 10% 90% tF, -OS -250mV 250mV
+SR -2.5V
FIGURE 1. LARGE SIGNAL WAVEFORM
FIGURE 2. SMALL SIGNAL WAVEFORM
Burn-In Circuit
HFA1110MJ/883 CERAMIC DIP
D4 V+ D2 C2 1
300
8 7 + 6 5 C1 D1 R2
2 3 4 R1
D3 V-
NOTES: R1 = 1k, 5% (Per Socket) R2 = 100, 5% (Per Socket) C1 = C2 = 0.01F (Per Socket) or 0.1F (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V 0.5V V- = -5.5V 0.5V
Spec Number 5
511083-883
HFA1110/883 Typical Design Information
The information contained in this section has been developed through characterization by Intersil and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RL = 100. Unless Otherwise Specified.
120 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 5ns/DIV 80 40 0 -40 -80 -120
1.2 0.8 0.4 0 -0.4 -0.8 -1.2
5ns/DIV
FIGURE 3. SMALL SIGNAL PULSE RESPONSE
2 1 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 -8 0 200M 400M 600M 800M 1G PHASE VOUT = 200mVP-P GAIN VOUT = 200mVP-P VOUT = 1VP-P
FIGURE 4. LARGE SIGNAL PULSE RESPONSE
+6 GAIN (dB) 0 PHASE (DEGREES) -45 -90 -135 -180 -225 -270 +3 0 -3 -6
RL = 1k RL = 100
RL = 50
0 -90 -180 RL = 1k 1M -270 -360 1G
FREQUENCY (Hz)
10M 100M FREQUENCY (Hz)
FIGURE 5. FORWARD GAIN AND PHASE
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
890 870 BANDWIDTH (MHz) 850 830 810 790 770 750 730 710
+2 +1 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 -8 1M 10M 100M FREQUENCY (Hz) 1G VOUT = 200mVP-P VOUT = 2.5VP-P VOUT = 4VP-P
-50
-30
-10
+10
+30
+50 +70
+90 +110 +130
TEMPERATURE (oC)
FIGURE 7. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
FIGURE 8. -3dB BANDWIDTH vs TEMPERATURE
Spec Number 6
511083-883
PHASE (DEGREES)
HFA1110/883 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RL = 100. Unless Otherwise Specified. (Continued)
+0.25 +0.20 +0.15 GAIN (dB) +0.10 +0.05 0 -0.05 -0.10 DEVIATION (DEGREES)
+2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 1M 10M FREQUENCY (Hz) 100M 200M 0 15 30 45 60 75 90 105 120 135 150
FREQUENCY (MHz)
FIGURE 9. GAIN FLATNESS
FIGURE 10. DEVIATION FROM LINEAR PHASE
50 -20 +135 PHASE (DEGREES) 40 INTERCEPT POINT (dBm)
-30 GAIN (dB) PHASE -40 GAIN
+90
30
+45
20
-50
0
10
-60 0 200M 400M
VOUT = 1VP-P 600M 800M 1G 0 0 50 100 150 200 250 FREQUENCY (MHz) 300 350 400
FREQUENCY (Hz)
FIGURE 11. REVERSE GAIN AND PHASE
FIGURE 12. 2 TONE, 3RD ORDER INTERMODULATION INTERCEPT
-30 -40
-30 -40 100 MHz DISTORTION (dBc) DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -5 -3 -1 1 3 5 7 9 11 13 50 MHz 30 MHz
-50 -60 -70
100 MHz
50 MHz -80 -90 -100 -5 -3 -1 1 3 5 7 9 11 13 30 MHz
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 13. 2ND HARMONIC DISTORTION vs POUT
FIGURE 14. 3RD HARMONIC DISTORTION vs POUT
Spec Number 7
511083-883
HFA1110/883 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RL = 100. Unless Otherwise Specified. (Continued)
21 18 SETTLING ERROR (%) OVERSHOOT (%) 0.8 0.4 0.2 0 -0.2 -0.4 -0.8 15 12 9 6 3 0 200 VO = 0.5VP-P VO = 1.0VP-P VO = 2.0VP-P
-5
0
5
10
15
20
25
30
35
40
45
300
400
500
600
700
800
900
1000
TIME (ns)
INPUT RISE TIME (ps)
FIGURE 15. SETTLING RESPONSE (VOUT = 1V)
FIGURE 16. OVERSHOOT vs INPUT RISETIME
+0.04
+0.02
RL = 200 RL = 100 RL = 1k
0
-0.02
-0.04 -3.0 -2.0 -1.0 0 +1.0 INPUT VOLTAGE (V) +2.0 +3.0
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 6 7 8 9 10 TOTAL SUPPLY VOLTAGE (V+ - V-, V)
FIGURE 17. INTEGRAL LINEARITY ERROR
25 24 SUPPLY CURRENT (mA) 23 22 21 20 19 18 17 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 TEMPERATURE (oC) BIAS CURRENT (A)
SUPPLY CURRENT (mA)
ERROR (%)
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 -60 -40 -20 0 +20 +40 +60 TEMPERATURE (oC) +80 +100 +120
FIGURE 19. SUPPLY CURRENT vs TEMPERATURE
FIGURE 20. BIAS CURRENT vs TEMPERATURE
Spec Number 8
511083-883
HFA1110/883 Typical Performance Curves
VSUPPLY = 5V, TA = 25oC, RL = 100. Unless Otherwise Specified. (Continued)
10 OUTPUT OFFSET VOLTAGE (mV) 9.8 9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8 7.8 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 OUTPUT VOLTAGE (V)
3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 |-VOUT |(RL = 50) |-VOUT |(RL = 100) +VOUT (RL = 100) +VOUT (RL = 50)
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 21. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE
100
200 NOISE CURRENT (pA/Hz)
NOISE VOLTAGE (nV/Hz)
80
160
60
120
40 INI 20 ENI 0 100 1K 10K
80
40
0 100K
FREQUENCY (Hz)
FIGURE 23. INPUT NOISE vs FREQUENCY
Spec Number 9
511083-883
HFA1110/883 PC Board Layout
The frequency response of this buffer depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Removing the GND plane under the output trace helps minimize this capacitance. An example of a good high frequency layout is the Evaluation Board shown in Figure 25.
Evaluation Board
The performance of this buffer may be evaluated using the HFA1110 Evaluation Board. The layout and schematic of the board are shown in Figure 25. To order evaluation boards, please contact your local sales office.
TOP LAYOUT
1
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the buffer's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 24 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the buffer bandwidth of 750MHz. By decreasing RS as CL increases (as illustrated in Figure 24), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve.
50 45 40 35 RS () 30 25 20 15 10 5 0 0 40 80 120 160 200 240 280 320 360 400 IN 50 4 5 10F -5V 0.1F +5V 0.1F 10F 1 2 HFA1110 3 6 8 7 RS 50 OUT
BOTTOM LAYOUT
FIGURE 25. EVALUATION BOARD SCHEMATIC AND LAYOUT
LOAD CAPACITANCE (pF)
FIGURE 24. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE
Spec Number 10
511083-883
HFA1110/883
TABLE 3. TYPICAL PERFORMANCE SPECIFICATIONS Device Characterized at: VSUPPLY = 5V, RL = 100, Unless Otherwise Specified PARAMETER Output Offset Voltage (See Note) Average Offset Voltage Drift Power Supply Rejection Ratio Input Current (See Note) Input Resistance Input Capacitance Input Noise Voltage (See Note) Input Noise Current (See Note) Input Common Mode Range Gain DC Non-Linearity (See Note) Output Voltage (See Note) VOUT = 2VP-P 2V Full Scale RL = 100 RL = 100 Output Current (See Note) RL = 50 RL = 50 DC Closed Loop Output Resistance Quiescent Supply Current (See Note) -3dB Bandwidth (See Note) Slew Rate Full Power Bandwidth (See Note) Gain Flatness (See Note) RL = Open VOUT = 200mVP-P VOUT = 5VP-P VOUT = 4VP-P To 30MHz To 50MHz To 100MHz Linear Phase Deviation (See Note) 2nd Harmonic Distortion (See Note) To 100MHz 30MHz, VOUT = 2VP-P 50MHz, VOUT = 2VP-P 100MHz, VOUT = 2VP-P 3rd Harmonic Distortion (See Note) 30MHz, VOUT = 2VP-P 50MHz, VOUT = 2VP-P 100MHz, VOUT = 2VP-P 3rd Order Intercept (See Note) 100MHz 300MHz 1dB Gain Compression 100MHz 150MHz 200MHz Reverse Isolation (S12) (See Note) 40MHz 100MHz 600MHz Rise and Fall Time Overshoot (See Note) Differential Gain Differential Phase VOUT = 0.5VP-P VOUT = 0.5VP-P, Input tR /tF = 600ps RL = 75, NTSC RL = 75, NTSC f = 100kHz f = 100kHz VCM = 0V Versus Temperature VSUP = 1.25V VCM = 0V VCM = 2V CONDITIONS TEMPERATURE (oC) 25 Full 25 25 25 25 25 25 Full 25 25 25 Full 25 to 125 -55 to 0 25 Full 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 TYPICAL 8 10 45 10 50 2.2 14 51 2.8 0.99 0.003 3.3 3.0 60 50 0.3 24 750 1250 150 0.01 0.02 0.03 0.3 -72 -57 -42 -80 -74 -51 30 10 14 10 7 -70 -60 -27 600 9 0.04 0.025 UNITS mV V/oC dB A k pF nV/Hz pA/Hz V V/V % V V mA mA W mA MHz V/s MHz dB dB dB Degrees dBc dBc dBc dBc dBc dBc dBm dBm dBm dBm dBm dB dB dB ps % % Degrees
NOTE: See Typical Performance Curves for more information.
Spec Number 11
511083-883
HFA1110/883 Die Characteristics
DIE DIMENSIONS: 63 x 44 x 19 mils 1 mils 1600 x 1130 x 483m 25.4m METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA GLASSIVATION: Type: Nitride Thickness: 4kA 0.5kA WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 at 47.5mA TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1110/883 NC
IN
V-
NC
NC
NC
NC
V+
OUT
Spec Number 12
511083-883
HFA1110/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c)
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c c1 D E e eA
e
DS
eA/2
c
aaa M C A - B S D S
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
eA/2 L Q S1
aaa bbb ccc M N
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 13
511083-

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